1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device. In particular, the present invention relates to a semiconductor device including a MIM element and a method of manufacturing the semiconductor device.
2. Description of the Related Art
Up to now, semiconductor devices including metal-insulator-metal (MIM) elements are described in JP 11-87650 A and JP 2007-49089 A.
JP 11-87650 A describes a semiconductor chip including a memory cell array region and a peripheral circuit region. In the peripheral circuit region of the semiconductor chip, first wiring layers connected with impurity semiconductor regions are formed on an upper surface of an interlayer insulating film. Upper portions of the first wiring layers are covered with cap insulating films. A spin-on-glass (SOG) film is formed on the cap insulating films over the entire surface of a substrate. The SOG film is polished by a chemical mechanical polishing (CMP) method to planarize the surface thereof. Therefore, according to JP 11-87650 A, a focus margin of a subsequent photolithography process can be improved. In the memory cell region, capacitor elements are formed in an upper layer than the polished SOG film.
JP 2007-49089 A describes a technology for improving the reliability of a MIM element even in the case where dishing occurs in a wiring or erosion occurs on an upper surface of the wiring when the MIM element is formed over the wiring. Specifically, the surface of an interlayer insulating film located on the wiring is planarized and then a lower electrode is formed, so the interlayer insulating film and the lower electrode become substantially flat. Therefore, even when a lower layer of the interlayer insulating film has unevenness, a capacitor element can be prevented from being affected by the unevenness. The technology described in JP 2007-49089 A has a predetermined effect on unevenness caused by recesses resulting from dishing or erosion on the upper surface of the wiring.
As a result of concentrated studies, the inventor(s) of the present invention found a new phenomenon that the reliability of the capacitor element formed over the wiring is reduced because of leakage or the like when protrusions such as hillocks are produced on the upper surface of the wiring.
Hereinafter, a point that protrusions such as hillocks are produced on the upper surface of the wiring in a wiring forming process is described with reference to a specific example.
FIGS. 7A, 7B, 7C, 8A, 8B, and 9 are cross-sectional views showing a process for manufacturing a semiconductor device. FIGS. 7A, 7B, 7C, 8A, 8B, and 9 show steps for forming a copper wiring by a damascene method and then forming a capacitor element over the copper wiring.
As shown in FIG. 7A, trenches are formed in a silicon oxide film (hereinafter, referred to as SiO2 film) 203 and then a barrier metal layer (not shown) for preventing copper diffusion is formed. Subsequently, the trenches are filled with copper by, for example, plating, and then polished by a CMP method to form a copper wiring 205.
Next, a diffusion prevention film 207 for covering the copper wiring 205 is formed on the SiO2 film 203 by a chemical vapor deposition (CVD) method (FIG. 7B), and then an SiO2 film 209 is laminated on the diffusion prevention film 207 (FIG. 7C). Examples of materials for the diffusion prevention film 207 include silicon carbonitride (hereinafter, referred to as SiCN) and silicon carbide (hereinafter, referred to as SiC). The SiO2 film 209 is polished by a CMP method (FIG. 8A). After that, a conductive film 245, an insulating film 247, and a conductive film 249 are formed in the stated order on the SiO2 film 209 (FIG. 8B) and processed into a predetermined shape to form a capacitor element 221 over the copper wiring 205 (FIG. 9). The capacitor element 221 includes a lower electrode 215, a capacitor insulating film 217, and an upper electrode 219.
When the diffusion prevention film 207 is to be formed by a CVD method during the manufacturing process, a silicon substrate (not shown) is normally heated at approximately 200° C. to 450° C. In this case, it is found that a part of an upper surface of the copper wiring 205 may protrude due to heating, thereby forming a protruding portion 235 (FIG. 7B).
When the protruding portion 235 is formed, a step portion 237 is provided corresponding to the shape of the protruding portion 235 at the time of formation of the diffusion prevention film 207. A cavity portion 241 or a recess portion 243 is provided in the SiO2 film 209 formed on the diffusion prevention film 207 (FIG. 7C). In some cases where such poor film formation of the SiO2 film 209 occurs, the upper surface of the SiO2 film 209 is not sufficiently planarized even after the SiO2 film 209 is polished by the CMP method, so a recess portion 239 is left (FIG. 8A). When the capacitor element 221 is to be formed while the recess portion 239 is left, as shown in FIGS. 8B and 9, a step portion 251, a step portion 253, and a step portion 255 are formed in the conductive film 245, the insulating film 247, and the conductive film 249, respectively. Therefore, it is likely to cause poor film formation in a part of the insulating film 247, that is, a part of the capacitor insulating film 217 or to reduce a withstanding voltage of the capacitor insulating film 217, thereby causing a leakage defect of the capacitor element 221.
As described above, when the capacitor element 221 is to be formed on the SiO2 film 209 while the SiO2 film 209 is not sufficiently planarized, the reduction in reliability, such as a reduction in withstanding voltage of a part of the capacitor insulating film 217 occurs. This causes a reduction in yield of the capacitor element 221 and the reduction in reliability thereof at the time of use.
In the case where the hillock-shaped protruding portion is produced, even when the technologies of JP 11-87650 A and JP 2007-49089 A which are described in “BACKGROUND OF THE INVENTION” are used, there is still room for improvement in terms of suppressing the reduction in reliability of the capacitor element.
JP 11-87650 A describes the technology for reducing the influence of a step having a relatively large curvature (global step) on an upper layer. The global step is formed in the vicinity of a boundary between the memory cell array region and the peripheral circuit region. Therefore, there is room for improvement in terms of eliminating a local step in the memory cell array region.
The technology described in JP 2007-49089 A is effective for recesses produced by dishing occurring during the CMP of the Cu wiring located under the MIM element, etching or erosion which is caused during cleaning after the CMP, or the like. However, when apart of the upper surface of the Cu wiring becomes a protrusion, the technology may be ineffective. Specifically, as described in JP 2007-49089 A, when the single-layer insulating film is formed on the diffusion prevention film and the surface thereof is planarized by a CMP method, it is necessary to excessively thicken the insulating film in order to eliminate an isolated protrusion such as the protruding portion 235. However, this is unrealistic. The insulating film formed on the protruding portion 235 has a defect just above the protruding portion 235, so a recess may become larger because of the chemical action of the CMP.